The present invention relates to an insulated gate field effect transistor, and more particularly to an insulated gate field effect transistor having a high drain breakdown voltage.
An insulated gate field effect transistor is essentially excellent as a high-speed power device for the reasons that thermal runaway would not occur because the temperature coefficient of the drain current is negative, that high-speed operation is possible since it is a majority carrier device, and that it has a high input resistance and a high power gain.
However, the drain breakdown voltage of the insulated gate field effect transistor, a typical example of which is an MOS transistor, and which has been heretofore used in an integrated circuit or the like, is as low as only about 50 to 60 V. Thus, in order to broaden the scope of the application as power devices of the MOS transistor it was essentially necessary to make it have a high drain breakdown voltage. In response to this requirement, high breakdown voltage MOS transistors of DSA structure, tetrode structure, offset gate structure, etc. have been proposed in the prior art. Among these proposed devices the offset gate MOS transistor is especially hopeful as a high breakdown voltage device for use in an integrated circuit because the structure is simple. With regard to the transistor having an offset gate structure, reference should be made, for example, to Journal of the Japan Society of Applied Physics, Vol. 44, Supplement 1975, pp. 249 to 255. In the offset gate MOS transistor, a low impurity concentration region of the same conductivity type as the drain is provided between a drain and a gate electrode, and upon application of a high drain voltage the low impurity concentration region becomes a depletion layer and thereby serves to raise the drain breakdown voltage.
Generally, a MOS field effect transistor comprises, in the case of an N-channel type, an N-type impurity region forming a source, a P-type region serving as a substrate and an N-type impurity region forming a drain, and such structure can be deemed to be an NPN bipolar transistor structure using the source as an emitter, the base as a substrate and the drain as a collector. In other words, one can consider that the above-mentioned NPN bipolar transistors is parasitic on such MOS field effect transistor.
It has been known that the effect of this parasitic bipolar device is remarkable in high breakdown voltage MOS transistors having a substrate of high specific resistance, and in shortchannel MOS transistor in which the shortness of the channel corresponds to a narrow base width of the parasitic bipolar transistor, and thus a negative resistance phenomenon appears in the drain voltage vs. drain current characteristics. Such a negative resistance phenomenon is explained to be the so-called parasitic bipolar effect that is generated by the fact that an avalanche breakdown of a PN-junction between drain and substrate is triggered and minority carriers in the bipolar operation are injected from the source region into the substrate, and it is especially remarkable in an N-type MOS transistor in which electrons having a large avalanche multiplying factor act as current carriers. Furthermore, in a high breakdown voltage MOS transistor, the substrate has a low impurity concentration, so as to raise the breakdown voltage of the PN-junction between the drain region and the substrate region. This corresponds to a rise in the base resistance in a bipolar parasitic bipolar transistor, and in such a case, the source-substrate PN-junction, that is, the emitter-base junction of the parasitic bipolar transistor can be easily forwardly biased even by a slight drain-substrate avalanche current, that is, collector-base current, and hence the negative resistance phenomenon becomes more and more liable to appear. Moreover, MOS transistors having a high breakdown voltage is generally used with a high drain voltage. Therefore, if current concentration occurs at a drain junction during the process of transition to the above-mentioned negative resistance condition, then a large power is applied to the junction, thereby readily resulting in thermal destruction. Such a phenomenon is disclosed in IEEE Transactions Electron Devices, Vol. ED-27, No. 2, February 1980, pages 395 to 398.
As an effective solution for preventing such negative resistance phenomena and thermal destruction phenomena, a high-resistance P-type silicon layer is epitaxially grown on a low-resistance P-type silicon body, and an N-channel MOS transistor is formed along the surface of the layer. In the device of the above-described structure, the avalanche-injected holes are absorbed by the low-resistance body section, and the rise of substrate potential in the proximity of the source region is suppressed, and thus the parasitic bipolar effect is removed.
However, for the realization of the above-described structure, the epitaxial growth of a high specific resistance silicon layer as thick as ten to twenty microns is necessitated, and this becomes one cause of the high cost of the devices. Moreover, in the case where it is desired to obtain an N-channel MOS transistor having a higher drain breakdown voltage, it is necessary to grow an even thicker epitaxial layer having a higher specific resistance that of than the above-mentioned example. According to present silicon epitaxial techniques, however, epitaxial growth of at most 20 to 30 microns in thickness is the practical limit, and because of a high specific resistance layer, even the control of impurity concentration of the order of 10.sup.14 cm.sup.-3 is not easy.
Accordingly, it has been difficult to realize an N-channel MOS transistor having a high breakdown voltage and an excellent characteristic which suppresses the negative resistance phenomena in a substrate consisting of a low-resistance P-type body and a high-resistance epitaxial layer grown on the body.